Substrate for IC package

Details Substrate for IC package Substrate for IC package

2007-07-10

2007-07-10

Clark, S. V. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S693000, C257S697000, C257S784000

Reexamination Certificate

active

11109734

ABSTRACT:
A packaging substrate is formed of an array of packaging units. Each packaging unit has a chip pad carrying a chip, a plurality of pins arranged around the chip pad and spaced from one another and the chip pad by an open space, an insulative member formed of a plurality of insulative member layers and filled up the open space, and a set of electrical elements, which includes a plurality of plated through holes cut through the insulative member layers, first lead wires embedded in the insulative member to electrically connect the plated through holes to one another, and second lead wires that connect the plated through holes to a respective adjacent pin.

REFERENCES:
patent: 5371029 (1994-12-01), Abdo et al.
patent: 5825084 (1998-10-01), Lau et al.
patent: 6441453 (2002-08-01), Tindle
patent: 6509560 (2003-01-01), Glenn et al.
patent: 6979897 (2005-12-01), Ma
patent: 7078791 (2006-07-01), Tindle et al.
patent: 2003/0085455 (2003-05-01), Roeters et al.
patent: 2006/0197234 (2006-09-01), Pape
patent: 0098114 (1984-01-01), None
patent: 60-7140 (1985-01-01), None

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