Integrated semiconductor memory with clock-synchronous...

Details Integrated semiconductor memory with clock-synchronous... Integrated semiconductor memory with clock-synchronous...

2007-07-17

2007-07-17

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S226000, C365S205000, C365S207000

Reexamination Certificate

active

11352393

ABSTRACT:
An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

REFERENCES:
patent: 6377512 (2002-04-01), Hamamoto et al.
patent: 2004/0169524 (2004-09-01), Maesaki et al.
patent: 2004/0184344 (2004-09-01), Saitoh et al.

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