1988-07-14
1989-09-19
Sikes, William L.
357233, 357 234, 357 44, H01L 2980, H01L 2978
Patent
active
048686204
ABSTRACT:
An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.
REFERENCES:
patent: 4485392 (1984-11-01), Singer
patent: 4611220 (1986-09-01), MacIver
D. Hodges and H. Jackson, "Analysis and Design of Digital Integrated Circuits", McGraw-Hill, NY, 1983, pg. 38.
Adler Michael S.
Kohl James E.
Pattanaya Deva N.
Scott Robert S.
Wildi Eric J.
Pacific Bell
Sikes William L.
Soltz David
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