Layout for NAND flash memory array having reduced word line...

Details Layout for NAND flash memory array having reduced word line... Layout for NAND flash memory array having reduced word line...

2007-07-24

2007-07-24

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185130, C365S051000, C365S063000, C365S230030, C365S185230

Reexamination Certificate

active

11480127

ABSTRACT:
A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and second memory sub-arrays have flash memory cells coupled to a plurality of word lines. A driver region separates the first and second regions and includes word line driver circuits coupled to the word lines of the first and second memory sub-arrays. A row decoder region adjacent the first region and separate from the driver region includes at least some sub-circuits of row decoder circuits located therein. The row decoder circuits are coupled to the word line driver circuits located in the driver region and are configured to activate driver circuits to drive word lines of the first and second memory sub-arrays in response to decoding address signals selecting the particular row decoder circuit.

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