Wafer level package, wafer level packaging procedure for...

Details Wafer level package, wafer level packaging procedure for... Wafer level package, wafer level packaging procedure for...

2007-05-08

2007-05-08

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S778000

Reexamination Certificate

active

10833149

ABSTRACT:
A wafer level packaging procedure provides a wafer having a pad mounting surface with bonding pads on the pad mounting surface. An insulative layer is formed with conductor formation holes exposing the bonding pads. Conductors are formed in the respective conductor formation holes. A photoresist protective layer is formed on the pad mounting surface and then holes are formed in the photoresist protective layer for exposing parts of the respective conductors. Conductive bumps are formed in the holes in the photoresist protective layer in electric connection to the respective conductors.

REFERENCES:
patent: 2004/0191955 (2004-09-01), Joshi et al.
patent: 2001-0009564 (2001-02-01), None
patent: 434848 (2001-05-01), None

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