Semiconductor device, word line driver circuit and word line dri

Details Semiconductor device, word line driver circuit and word line dri Semiconductor device, word line driver circuit and word line dri

1998-02-23

2000-04-04

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518909, 365194, G11C 800

Patent

active

060469560

ABSTRACT:
A semiconductor memory device comprises a memory cell array having a plurality of memory cells arranged in a row/column array, a plurality of word lines for selecting any row in the memory cell array, and a word line driver circuit for selectively activating/deactivating the word lines. The word line driver circuit has a first discharge circuit for discharging a charge on any word line to a first reference potential at a first stage for deactivating any word line and a second discharge circuit for discharging the word line which is discharged to the first reference potential to a second reference potential at a second stage which is lower than the first reference potential. In accordance with this circuit arrangement, a charge on the word line is not discharged all at one time and can be discharged stepwise. Therefore, only a smaller current drive capability is required than when the charge on the word line is discharged to the second reference potential all at one time.

REFERENCES:
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T. Tsuruda et al, "High-speed/High-band Width Design Methodologies for on Chip DRAM Core Multimedia System LSIs," in CICC Dig. Tech. Papers. May 1996, pp 265-268.

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