Double bootstrapped clock buffer circuit

Details Double bootstrapped clock buffer circuit Double bootstrapped clock buffer circuit

1983-09-26

1985-09-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307481, 307269, 307270, H03K 1706, H03K 19096

Patent

active

045423075

ABSTRACT:
A buffer circuit has first and second boot-strap circuits. The first boot-strap circuit charges the gate of an output MOS transistor to a voltage above a supply voltage when an input signal has a first logic level. The gate of a precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit so as to precharge a capacitor in the first boot-strap circuit to a voltage above the supply voltage when the input signal has a second logic level.

REFERENCES:
patent: 3714466 (1973-01-01), Spence
patent: 3778784 (1973-12-01), Karp et al.
patent: 3898479 (1975-08-01), Proebsting
patent: 3937983 (1976-02-01), Reed
patent: 3988617 (1976-10-01), Price
patent: 4049979 (1977-09-01), Shieu et al.
patent: 4354123 (1982-10-01), Eaton, Jr.
patent: 4431927 (1984-02-01), Eaton, Jr. et al.
patent: 4494018 (1985-01-01), Clemen et al.
Sonoda, "MOSFET Powering Circuit", IBM Tech. Disc. Bull., vol. 13, No. 9, Feb. 1971, p. 2658.
Arzubi et al., "Bootstrap Driver Stage", IBM Tech. Disc. Bull., vol. 23, No. 9, Feb. 1981, pp. 4185-4186.

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