Semiconductor memory device having a sense amplifier region form

Details Semiconductor memory device having a sense amplifier region form Semiconductor memory device having a sense amplifier region form

1999-06-18

2000-04-04

Tran, Andrew Q.

Static information storage and retrieval

Format or disposition of elements

36523003, 365208, 365202, 365203, G11C 502

Patent

active

060469242

ABSTRACT:
Sub-cell arrays are formed in p-type cell-forming wells, respectively, with a region between two adjacent sub-cell arrays being formed a sense amplifier circuit region which includes three wells, a first p-type well isolated from the p-type cell-forming wells, and first and second n-type wells for isolating the p-type cell-forming wells, wherein an NMOS sense amplifier is arranged in the first p-type well, a PMOS sense amplifier and a first switch circuit are arrange in one of the first and second n-type wells and a bit line equalizer circuit and a second switch circuit are arranged in the other of the first and second n-type well.

REFERENCES:
patent: 5774408 (1998-06-01), Shirley et al.
patent: 5875141 (1999-02-01), Shirley et al.

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