Static information storage and retrieval – Floating gate
Reexamination Certificate
2006-12-26
2006-12-26
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
C365S185170, C365S185100
Reexamination Certificate
active
07154779
ABSTRACT:
A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.
REFERENCES:
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5043940 (1991-08-01), Harari
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5373465 (1994-12-01), Chen et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5677872 (1997-10-01), Samachisa et al.
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5867429 (1999-02-01), Chen et al.
patent: 5877980 (1999-03-01), Mang et al.
patent: 5890192 (1999-03-01), Lee et al.
patent: 5930167 (1999-07-01), Lee et al.
patent: 5936887 (1999-08-01), Choi et al.
patent: 5990514 (1999-11-01), Choi et al.
patent: 6044017 (2000-03-01), Lee et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6093605 (2000-07-01), Mang et al.
patent: 6103573 (2000-08-01), Harari et al.
patent: 6121654 (2000-09-01), Likharev
patent: 6136652 (2000-10-01), Hazani
patent: 6151248 (2000-11-01), Harari et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6246607 (2001-06-01), Mang et al.
patent: 6461905 (2002-10-01), Wang et al.
patent: 6617639 (2003-09-01), Wang et al.
patent: 6642066 (2003-11-01), Halliyal et al.
patent: 6784484 (2004-08-01), Blomme et al.
patent: 6790782 (2004-09-01), Yang et al.
patent: 2003/0002348 (2003-01-01), Chen et al.
patent: 2005/0138262 (2005-06-01), Forbes
patent: 0105802 (1984-04-01), None
patent: 59147461 (1984-08-01), None
“An Empeirical Model for Charge Leakage Through Oxide-Nitride-Oxide Interpoly Dielectric in Stacked-Gate Flash Memory Devices”, Jang Han Kim, Jung Bum Choi, Bong Jo Shin and Kuen Hyung Park, Semiconductor Science and Technology 18 (2003) pp. 258-165.
Borson, et al., “Direct Measurement of the Energy Distribution of Hot Electrons in Silicon Dioxide,” J. Appl. Phys., vol. 58, No. 3.1, Aug. 1985, pp. 1302-1313.
Brown, et al.,“Nonvolatile Semiconductor Memory Technology, A Comprehensive Guide to Understanding and Using NVSM Devices,” IEEE, pp. 198-200.
Camm, et al., “Engineering Ultra-Shallow Junctions Using IRTP™,” IEEE, Vortek Industries Limited, 2002.
Chan, et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.
Choi, et al., “A Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance,” IEEE Symposium on VLSI Technology Digest of Technical Papers, 1996, pp. 238-239.
Choi, et al., “A Triple Polysillcon Stacked Flash Memory Cell With Wordline Self-Boosting Programming”, IEEE, 1997, pp. 283-286.
Dijkstra, et al., “ISSG RTO (In-situ Steam Generation Rapid Thermal Oxidation) Grown Tunnel Oxide for Improved Reliability of Flash Memories,” Philips Semiconductors, pp. 85-86.
Dimaria, “Graded or Stepped Energy Band-Gap-Insulator MIS Structures (GI-MIS or SI-MIS),” American Institute of Physics, Sep. 1979, pp. 5826-5828.
DiMaria, et al., “Dual-Electron-Injector-Structure Electrically Alterable Read-Only-Memory Modeling Studies,” IEEE Transactions on Electron Devices, vol. ED-28, No. 9, Sep. 1981, pp. 1047-1053.
DiMaria, et al., “Electrically-Alterable Memory Using A Dual Electron Injector Structure,” IEEE Electron Device Letters, vol. EDL-1, No. 9, Sep. 1980, pp. 179-180.
DiMaria, et al., “Extended Cyclability in Electrically-Alterable Read-Only-Memories,” IEEE Electron Device Letters, vol. EDL-3, No. 7, Jul. 1982, pp. 191-195.
Hirayama, et al., “Low-Temperature Growth of High-Integrity Silicon Oxide Films by Oxygen Radical Generated in High-Density Krypton Plasma,” IEEE, 1999, pp. 10.3.1-10.3.4.
Kim, et al., “Fast Parallel Programming of Multi-Level NAND Flash Memory Cells Using the Booster-Line Technology”, Symposium on VLSI Technology Digest of Technical Papers, 1997, pp. 65-66.
Konstantin, et al., “Riding the Crest of a New Wave in Memory, NOVORAM: A new Concept for Fast, Bit-Addressable Nonvolatile Memory Based on Crested Barriers,” Circuits and Devices, Jul. 2000, p. 17.
Kotecha, et al., “WAM 3.2: A Dual-Gate Floating Gate FET Device,” IEEE International Solid-State Circuits Conference, 1981, pp. 38-39.
Korotkov, et al., “Resonant Fowler-Nordheim Tunneling through Layered Tunnel Barriers and its Possible Applications,,”1999 IEEE, 0-7803-5413-3/99.
Lee, et al., “Effects of Floating Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, p. 264.
Nozaki, et al., “A 1-Mb EEPROM With NONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 497-501.
Ohmi, et al., “New Paradigm of Silicon Technology,” Proceedings of the IEEE, vol. 89, No. 3, Mar. 2001, pp. 394-412.
Ohtsubo, et al., “Low Temperature Growth (400° C.) of High-Integrity Thin Silicon-Oxynitride Films by Microwave-Excited high-Denisty Kr/O2/NH3 Plasma,” pp. 166-169.
Satoh, et al., “A Novel Channel Boost Capacitance (CBC) Cell Technology with Low Program Disturbance Suitable for Fast Programming 4Gbit NAND Flash Memories”, IEEE Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 108-109.
Satoh, et al., “A Novel Gate-Offset NAND Cell (GOC-NAND) Technology Suitable for High-Denisty and Low-Voltage-Operation Flash Memories,” Technical Digest of 1999 IEDM, section 11, No. 2, p. 275.
Seidel, et al., “Progress and Challenges for ALD Applications,”Genus, Inc., Aug. 5, 2003, pp. 1-39.
Sekine, et al., “Highly Reliable Ultrathin Silicon Oxide Film Formation at Low Temperature by Oxygen Radical Generated in High Density Krypton Plasma,” IEEE Transactions on Electron Devices, vol. 48, No. 8, Aug. 2001, pp. 1550-1555.
Suh, et al., “A 3.3V 32 Mb NAND Flash Memory With Incremental Step Pulse Programming Scheme,” IEEE international Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1995. pp. 94-95, 305-306, 128-129, and 350.
Yu, et al., “Energy gap and band allignment for (HIO2)x(AI2O3)1-x on (100) SI,” Applied Physics Letters, Vol. 81, No. 2, Jul. 8, 2002, pp. 376-378.
Buckley, et al., “Engineering of ‘Conduction Band-Crested Barriers’ or ‘Dielectric Constant-Crested Barriers’ in view of their application to floating-gate non-volatile memory devices,” pp. 55-56.
Lutze Jeffrey W.
Mokhlesi Nima
Hoang Huan
Sandisk Corporation
Vierra Magen Marcus & DeNiro LLP
LandOfFree
Non-volatile memory cell using high-k material inter-gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory cell using high-k material inter-gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory cell using high-k material inter-gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3710877