Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185240

Reexamination Certificate

active

07002848

ABSTRACT:
This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of “write processing” and “upper limit determination processing” to each threshold voltage distribution, after the end of write processing for “10” and “00” distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the “10” and “00” distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are not masked.

REFERENCES:
patent: 5898621 (1999-04-01), Takahashi et al.
patent: 5999445 (1999-12-01), Rolandi et al.
patent: 6046936 (2000-04-01), Tsujikawa et al.
patent: 6078519 (2000-06-01), Kanamitsu et al.
patent: 6081453 (2000-06-01), Iwahashi
patent: 11-232886 (1999-08-01), None
patent: 11-345494 (1999-12-01), None
patent: 2001-23383 (2001-01-01), None

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