Method for manufacturing shallow trench isolation in...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S435000, C438S437000, C438S770000, C438S773000

Reexamination Certificate

active

06998326

ABSTRACT:
The method for manufacturing a shallow trench isolation (STI) in a semiconductor device with an enhanced gap-fill property and without a detrimental effect of fluorine by introducing a two-stage thermal process. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming a trench structure in the semiconductor substrate; forming a hydrogen (H2)-based high density plasma (HDP) oxide layer over a first resultant structure; forming a nitrogen trifluoride (NF3)-based HDP oxide layer into the trench structure with a predetermined depth; carrying out a two-stage thermal process for removing fluorine in the NF3-based HDP oxide layer; and forming a helium (He)-based HDP oxide layer over a second resultant structure.

REFERENCES:
patent: 6261975 (2001-07-01), Xia et al.
patent: 6387764 (2002-05-01), Curtis et al.
patent: 6660613 (2003-12-01), Kim et al.
patent: 6849520 (2005-02-01), Kim et al.
patent: 2003/0045070 (2003-03-01), Kim et al.
patent: 2004/0082143 (2004-04-01), Kim et al.

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