Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-02-28
2006-02-28
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185030, C365S185220, C365S185110
Reexamination Certificate
active
07006380
ABSTRACT:
A non-volatile semiconductor memory device includes: a memory cell array in which a plurality of electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to write M-value data (where, M is an integer equal to 4 or more) to pair-cells each constituted by simultaneously selected first and second memory cells connected to a pair of bit lines in the memory cell array, the M-value data being defined as a combination of different threshold levels of the first and second memory cells in M threshold levels to be set at each memory cell, and read M-value data stored in each pair-cell by sensing a difference between cell currents of the first and second memory cells; and a controller configured to control data write and read operations for the memory cell array.
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patent: 6525979 (2003-02-01), Kato
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patent: 6847555 (2005-01-01), Toda
Kabushiki Kaisha Toshiba
Tran Andrew Q.
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