Coarse tuning for fractional-N synthesizers

Details Coarse tuning for fractional-N synthesizers Coarse tuning for fractional-N synthesizers

2006-06-20

2006-06-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C331S016000, C331S00100A

Reexamination Certificate

active

07064591

ABSTRACT:
An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

REFERENCES:
patent: 3538450 (1970-11-01), Andrea et al
patent: 4875046 (1989-10-01), Lewyn
patent: 4918403 (1990-04-01), Martin
patent: 5117206 (1992-05-01), Imamura
patent: 5235335 (1993-08-01), Hester et al.
patent: 5337024 (1994-08-01), Collins
patent: 5493715 (1996-02-01), Humphreys et al.
patent: 5635875 (1997-06-01), Kusakabe
patent: 5973633 (1999-10-01), Hester
patent: 5977836 (1999-11-01), Swan et al.
patent: 6226499 (2001-05-01), Nakatani et al.
patent: 6509800 (2003-01-01), Stockton
patent: 6560452 (2003-05-01), Shealy
patent: 6693468 (2004-02-01), Humphreys et al.
patent: 6710664 (2004-03-01), Humphreys et al.
patent: 6724265 (2004-04-01), Humphreys
patent: 6731145 (2004-05-01), Humphreys et al.
patent: 6778022 (2004-08-01), Zhang et al.
patent: 6806786 (2004-10-01), Lam et al.
patent: 6838951 (2005-01-01), Nieri et al.
patent: 6850749 (2005-02-01), Soorapanth et al.
patent: 6937668 (2005-08-01), Sridharan et al.
patent: 2005/0036580 (2005-02-01), Rana
patent: 6-77820 (1994-03-01), None
Abele et al., “20mW SiGe-MMIC-VCO at 5GHz with Integrated 4:1 Divider for User in a PLL,” Dept. of Electron Devices and Circuits, University of Ulm, Germany, 2001.
Dunning et al., “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 412-422.
Koo et al., “A Fully Integrated CMOS Frequency Synthesizer With Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems,” IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 536-542.
Koo et al., “A Fully-Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems,” 2001 Symposium VLSI Circuits Digest of Technical Papers, 2001, pp. 43-46.
Kral et al., “RF-CMOS Oscillators with Switched Tuning,” Proceedings of the Custom IC Conference, Santa Clara, CA, May 1998, pp. 555-558.
Wilson et al., “A CMOS Self-Calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000, pp. 1437-1444.

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