Semiconductor memory device having different synchronizing...

Details Semiconductor memory device having different synchronizing... Semiconductor memory device having different synchronizing...

2006-10-31

2006-10-31

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080, C365S193000

Reexamination Certificate

active

07130241

ABSTRACT:
A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver. The clock buffer receives an external clock signal and information about a column address strobe (CAS) latency and generates either a first clock signal which synchronizes with rising edges of the external clock signal or a second clock signal which synchronizes with falling edges of the external clock signal depending on the type of CAS latency information. The column selection line decoder receives and decodes a column selection address and outputs a decoding address used to select either a column selection line signal synchronized with the first or second clock signal. The control signal generation circuit outputs control signals that synchronize with one of the first and second clock signals. The column selection line driver drives the column selection line signal in synchronization with one of the first and second clock signal in response to the decoding address and the control signals.

REFERENCES:
patent: 6404697 (2002-06-01), Ryu et al.
patent: 6552955 (2003-04-01), Miki
patent: 6813696 (2004-11-01), Kanda et al.
patent: 2001-0035850 (2001-05-01), None

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