Circuit including a latching unit for holding instructions durin

Details Circuit including a latching unit for holding instructions durin Circuit including a latching unit for holding instructions durin

1993-04-14

1995-05-30

Kim, Ken S.

Boots, shoes, and leggings

3642292, 3642476, 3642616, 3642632, 3642701, 364DIG1, 3649411, 3642302, 3642628, 395375, G06F 922

Patent

active

054210216

ABSTRACT:
A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstrictions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means. The exception handling floating-point microinstruction received from the control memory is not stored in the second latching means. The exception handler floating point microinstruction stored in the first latching means is executed. The floating point microinstruction stored in the second latching means is executed. A method for allowing floating point instructions to be executed in a microprocessor in parallel with non-floating point instructions is also described. Circuitry allowing floating point instructions to be executed in parallel with non-floating point instructions is also described.

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