Delay locked loop using synchronous mirror delay

Details Delay locked loop using synchronous mirror delay Delay locked loop using synchronous mirror delay

2006-12-12

2006-12-12

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

07148729

ABSTRACT:
A delay locked loop comprises a circuit configured to receive a clock signal, divide the clock signal by two to provide a divided clock signal, and mirror with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal.

REFERENCES:
patent: 6236251 (2001-05-01), Akamatsu
patent: 2003/0034815 (2003-02-01), Lin

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