Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-12-26
2006-12-26
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S072000, C345S082000, C345S098000, C345S204000
Reexamination Certificate
active
07154455
ABSTRACT:
A gate line GL is set to an H level to switch on a selection TFT (10) and a short-circuiting TFT (16). A current corresponding to data (data current (negative)) is applied to a data line (Data). In this manner, a current corresponding to the data current flows through a voltage converter TFT (12) and a driver TFT (14) and light is emitted from an organic EL element (50). A gate voltage of the voltage converter TFT (12) and the driver TFT (14) in this process is stored in a storage capacitor (C). Even after the data current is switched off and the selection TFT (10) and the short-circuiting TFT (16) are switched off, the driver TFT (14) continues to apply a current. After a predetermined emission period elapses, an erase line (ESL) is driven to switch an erase TFT (18) on to discharge the storage capacitor (C) and switch the driver TFT (14) off.
REFERENCES:
patent: 6570338 (2003-05-01), Bae
patent: 6583775 (2003-06-01), Sekiya et al.
patent: 6954194 (2005-10-01), Matsumoto et al.
Machio, Yamagishi “Display Device” Japanese Patent No.: JP02001147659A (Publication Date: May 29, 2001). Application No.: JP11327637 (Application Date: Nov. 18, 1999). Assignee: Sony Corp.
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A copy of Office Action for corresponding Chinese Patent Application No. 03155959X with its English translation. A copy of Korean Patent Patent Laid-Open Publication No. 2001-77572 and its English Abstract.
A copy of Chinese Patent Publication No. 1278635A and its English Abstract.
Hjerpe Richard
Pham Tammy
Sanyo Electric Co,. Ltd.
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