Microprocessor with memory storing instructions for time-compres

Details Microprocessor with memory storing instructions for time-compres Microprocessor with memory storing instructions for time-compres

1995-02-01

1997-04-15

Lim, Krisna

G06F 930, G06F 938

Patent

active

056219075

ABSTRACT:
A microcomputer includes an instruction decoder and a program counter. The instruction decoder decodes fetched instructions and outputs a control signal ordering execution of the fetched instruction. The control signal from the instruction decoder includes a component controlling fetch cycles which triggers a fetch cycle at the beginning of each instruction cycle to fetch the operand for the instruction currently being executed and midway through each instruction cycle to fetch the OP code for the next instruction. The program counter is responsive to the triggering of each fetch cycle to increment its counter value so as to keep the counter value consistent with the address being accessed in each fetch cycle.

REFERENCES:
patent: 4462073 (1984-07-01), Grondalski
patent: 4654781 (1987-03-01), Schwartz et al.
Mano, M. Morris; "Computer System Architecture" pp. 244-245, 264-279 290-323; 1982.

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