Semiconductor memory device having a back gate voltage controlle

Details Semiconductor memory device having a back gate voltage controlle Semiconductor memory device having a back gate voltage controlle

1998-11-24

2000-03-07

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365207, 36518909, G11C 800

Patent

active

060349204

ABSTRACT:
A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V.sub.BB) and has a reduced dependency on a high voltage supply (V.sub.DD) of the memory device.

REFERENCES:
patent: 5768214 (1998-06-01), Saitoh et al.

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