Semiconductor device fabrication method

Details Semiconductor device fabrication method Semiconductor device fabrication method

2006-11-21

2006-11-21

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S117000, C702S182000, C702S189000, C700S121000, C438S005000, C438S010000, C438S014000, C324S500000, C324S071500, C714S025000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07139671

ABSTRACT:
A semiconductor device fabrication method comprises; a first step S1of fabricating a plurality of semiconductor chips on a plurality of semiconductor wafers, respectively; a second step S4of making a probe test on the plural semiconductor chips respectively, which are present in a sampling region of one semiconductor wafer of the plural semiconductor wafers; and the third step S5of computing a yield of the plural semiconductor chips present in the sampling region, when the yields of the plural semiconductor chips computed in the third step are a reference value or above, the probe test is not made on the plural semiconductor chips, which are present outside the sampling region of said one semiconductor wafer and on the rest semiconductor wafers of the plural semiconductor wafers fabricated in the same lot as said one semiconductor wafer. The probe test is made on the plural semiconductor chips respectively, which are present in the sampling region of said one semiconductor wafer of the plural semiconductor wafers, and when the yield of the semiconductor chips present in the sampling region is the reference value or above, the probe test is not made on the rest semiconductor chips present in the rest region of said one semiconductor wafer other than the sampling region and on the rest semiconductor wafers fabricated in the same lot as said one semiconductor wafer, whereby the inspection period of time can be drastically shortened.

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