Static information storage and retrieval – Floating gate – Particular connection
Patent
1999-06-15
2000-03-07
Tran, Andrew Q.
Static information storage and retrieval
Floating gate
Particular connection
36518531, 3651851, 36518518, 36518527, 365187, 365188, 257318, 257319, 257320, 257322, G11C 1604
Patent
active
060348933
ABSTRACT:
A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.
REFERENCES:
patent: 5646901 (1997-07-01), Sharpe-Geisler et al.
patent: 5666309 (1997-09-01), Peng et al.
patent: 5748525 (1998-05-01), Wong et al.
U.S. Application No. 09/334,051 filed Jun. 15, 1999 by Mehta et al., entitled "Zero-Power CMOS Nonvolatile Memory Cell Having an Avalanche Injection Element", now allowed.
Tran Andrew Q.
Vantis Corporation
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