Transistor stack read only memory

Details Transistor stack read only memory Transistor stack read only memory

1998-04-15

2000-03-07

Yoo, Do Hyun

Static information storage and retrieval

Read only systems

Semiconductive

365104, 36518505, 36518902, 365203, G11C 700

Patent

active

06034881&

ABSTRACT:
The present invention, generally speaking, provides compact ROM layouts for trace or via-programmable (e.g., metal programmable) using transistor stacks. A number of field effect transistors (for example, eight) are coupled in series. For a particular transistor, a logic zero is programmed by forming a metal trace between the source and drain of the transistor. To read out the value of a particular bit, a logic zero is applied to the gate of the corresponding transistor. Logic ones are applied to the gates of the remaining transistors in the stack. A logic one precharge signal is applied to the top and bottom of the stack. A logic zero is then applied to the bottom of the stack. The logic zero reaches a sense amplifier coupled to the top of the transistor stack only if there is a short circuit across the transistor being read, indicating a logic zero bit value. Otherwise, the precharged logic one condition remains. Transistor stacks may be paired in a similar manner as individual transistors in conventional layouts. A very efficient ROM layout results.

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