Method for forming a self-aligned source/drain contact for an MO

Details Method for forming a self-aligned source/drain contact for an MO Method for forming a self-aligned source/drain contact for an MO

1988-03-23

1989-09-19

Lacey, David L.

Fishing, trapping, and vermin destroying

437189, 437195, 437 41, 437228, 156643, 156644, H01L 21265, H01L 21283, H01L 21308

Patent

active

048681385

ABSTRACT:
A process for forming electrical interconnect on MOS semiconductor integrated circuits includes the formation of a capping layer of oxide over the first level poly layer prior to patterning. The capping layer is then removed over selected regions. The conductive layer and capping oxide layer are then patterned to form transistor gates and interconnect. Source/drain regions are formed in active areas of the integrated circuit, and sidewall oxide is formed next to the patterned gate regions. When a second layer of interconnect is formed and patterned over the integrated circuit, contact between the first and second interconnect layers is made in the previously defined selected regions.

REFERENCES:
patent: 4288256 (1981-09-01), Ning et al.
patent: 4610078 (1986-09-01), Matsukawa et al.
patent: 4640000 (1987-02-01), Sato
patent: 4727038 (1988-02-01), Watabe et al.

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