Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-08-15
2006-08-15
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260, C365S185180
Reexamination Certificate
active
07092297
ABSTRACT:
The present invention provides a method for erasing floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for erasing an array of non-volatile flash memory cells arranged in a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the plurality of rows. The embodiment of the method begins by applying a positive voltage to odd word lines in the plurality of word lines in a first phase of an erase cycle. The plurality of word lines comprising alternating odd and even word lines. The embodiment continues by applying a negative voltage to even word lines in the plurality of word lines in the first phase of the erase cycle. Then, the embodiment applies the negative voltage to the odd word lines in the plurality of word lines in a second phase of said erase cycle. Thereafter, the embodiment continues by applying the positive voltage to the even word lines in the second phase of the erase cycle.
REFERENCES:
patent: 5856942 (1999-01-01), Lee et al.
patent: 6005810 (1999-12-01), Wu
patent: 6580643 (2003-06-01), Satoh et al.
patent: 6930928 (2005-08-01), Liu et al.
Advanced Micro Devices , Inc.
Lam David
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