Excavating
Patent
1994-05-11
1995-05-30
Canney, Vincent P.
Excavating
371 223, G06F 1100
Patent
active
054208696
ABSTRACT:
A semiconductor integrated circuit device includes an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal, an input circuit which is connected to the external connection terminal and receives the normal signal via the external connection terminal, an n-channel field effect transistor having a gate connected to the external connection terminal, a drain coupled to a first voltage line via a load element, and a source connected to a second voltage line. The second voltage line is at a potential approximately equal to said high potential. The first voltage line is at a potential equal to or higher than the sum of the high potential and a threshold voltage of the n-channel field effect transistor. The test mode setting signal of a potential equal to or higher than the sum of the high potential and the threshold voltage is applied to the n-channel field effect transistor. A test mode setting signal detecting signal used to initiate a test of the semiconductor integrated circuit device is output via the drain of the n-channel field effect transistor.
REFERENCES:
patent: 4558232 (1985-12-01), Simpson
patent: 4970727 (1990-11-01), Miyawaki et al.
patent: 5170077 (1992-12-01), Schreck
patent: 5341096 (1994-08-01), Yamamura
Canney Vincent P.
Fujitsu Limited
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