Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2006-02-28
2006-02-28
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C257S314000, C438S257000, C438S267000
Reexamination Certificate
active
07005328
ABSTRACT:
A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.
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Ebina Akihiko
Inoue Susumu
Le Thao P.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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