Methods for renaming stack references to processor registers

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S217000

Reexamination Certificate

active

07085914

ABSTRACT:
According to one aspect of the invention, there is provided a method for renaming memory references to stack locations in a computer processing system. The method includes the steps of detecting stack references that use architecturally defined stack access methods, and replacing the stack references with references to processor-internal registers. The architecturally defined stack access methods include memory accesses that use one of a stack pointer, a frame pointer, and an argument pointer. Moreover, the architecturally defined stack access methods include push, pop, and other stack manipulation operations.

REFERENCES:
patent: 3737871 (1973-06-01), Katzman
patent: 5659703 (1997-08-01), Moore et al.
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5838941 (1998-11-01), Valentine et al.
patent: 5872990 (1999-02-01), Luick et al.
patent: 5911057 (1999-06-01), Shiell
patent: 5926832 (1999-07-01), Wing et al.
patent: 5953741 (1999-09-01), Evoy et al.
patent: 6286095 (2001-09-01), Morris et al.
Hamacher et al., Computer Organization, 1978, McGraw-Hill, Inc., second edition, pp. 112-114.
Austin, et al., “Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency”, IEEE Proceedings of MICRO-28, Nov. 1995, pp. 82-92.
Lamport, “How to Make a Multiprocessor Computer Than Correctly Executes Mulitprocess Programs”, IEEE Transaction on Computers, vol. C-28, No. 9, Sep. 1979.
Adve, et al., “Shared Memory Consistency Models: A Tutorial”, Tech. Rpt. 9512, Dept. Of Elect. And Computer Eng., Rice University, pp. 1-23, Sep. 1995.
Postiff, et al., “The Limits of Instruction Level Parallelism in SPEC95 Appliations”, Int. Conf. On Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Workshop on Interaction Between Compilers and Computer Architecture, Oct. 1998.
Franklin, et al., “ARB: A Hardware Mechanism for Dynamic Reordering of Memory References”, IEEE Transactions on Computers, vol. 45, No. 5, May 1996, pp. 552-571.
Moshovos, et al., “Streamlining Inter-operation Memory Communication via Data Dependence Prediction”, IEEE Proc. Of 30thAnnual Symposium on Microarchitecture Research, Triangle Park, N. Carolina, pp. 235-245, Dec. 1997.
Tyson, et al., “Improving the Accuracy and Performance of Memory Communication Through Renaming”, 1997 IEEE Proc. Of 30thAnnual Symposium on Microarchitecture Research, Triangle Park, N. Carolina, pp. 218-227, Dec. 1997.
Mahlke, et al., “Sentinel Scheduling for VLIW and Superscaler Process”, Int. Conf. On Architectural Support for Programming Languages and Operating Systems, (ASPLOS V), MA, USA, pp. 238-247, Oct. 1992.
UNIX Systems for Modern Architectures, Addison Wesley, pp. 285-349, Sep. 1994.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods for renaming stack references to processor registers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for renaming stack references to processor registers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for renaming stack references to processor registers will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3681643

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.