Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2006-02-14
2006-02-14
Paladini, Albert W. (Department: 2125)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S014000, C716S030000
Reexamination Certificate
active
06999910
ABSTRACT:
The present invention is directed to a comprehensive design flow system. A system and method are provided that provide a comprehensive system to introduce a metamethodology that integrates EDA design tools into a manageable and predictable design flow. A method of designing an integrated circuit may include accessing a design utility operating on an information handling system, displaying a dynamic template on a display device of an information handling system, wherein the dynamic template implements at least two symbols displayable on a display device, in which the at least two symbols each correspond to a respective EDA tool, and arranging the at least two symbols displayed on the display device. The at least two symbols are arranged to indicate an interrelationship of the EDA tools in a design process of an integrated circuit.
REFERENCES:
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 5625565 (1997-04-01), Van Dyke
patent: 6026226 (2000-02-01), Heile et al.
patent: 6253358 (2001-06-01), Takahashi
patent: 6269467 (2001-07-01), Chang et al.
patent: 6574778 (2003-06-01), Chang et al.
patent: 6634008 (2003-10-01), Dole
patent: 6678875 (2004-01-01), Pajak et al.
patent: 6704917 (2004-03-01), Curran et al.
patent: 6721922 (2004-04-01), Walters et al.
patent: 6742165 (2004-05-01), Lev et al.
patent: 6834380 (2004-12-01), Khazei
patent: 2003/0097241 (2003-05-01), Koford et al.
patent: 2004/0025119 (2004-02-01), Hamlin
“A rule based VLSI process flow validation system with macroscopic process simulation”, IEEE Transactions on semiconductor manufacturing, vol. 3, No. 4, Nov. 1990, oages 239-246—Author(s)—Funakoshi et al.
“Rapid Chip Management System”; filed Nov. 20, 2002; U.S. Appl. No. 10/301,182—Author(s)—Daniel M. Weed.
Simplify Programmable-Logic-IP Integration—Author(s)—Cravotta, Robert.
Altera Casts Spotlight On IP Integration Tool—Author(s)—Souza, Crista.
Hamlin Christopher L.
Koford James S.
LSI Logic Corporation
Paladini Albert W.
Suiter West Swantz pc llc
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