Data bus buffer control circuit

Details Data bus buffer control circuit Data bus buffer control circuit

1986-04-14

1988-11-29

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300

Patent

active

047886609

ABSTRACT:
A data bus buffer control circuit which is capable of delaying a data bus buffer output for a period corresponding to an arbitrary number of clock periods. A counter provided at an output of a write data output delay selection device is presettable by a read/write signal during read periods so that the number of clock periods to be preset is varied according to a desired delay. The counter counts the clock signal supplied through a logic circuit after commencement of the write cycle. When the content of the counter reaches the desired value, it provides an output by which the data bus buffer is enabled. Since the delay of the write data output is set every read cycle, it is possible to provide an optimum delay of the write data output for an accessed device and to interface low speed devices by increasing the number of bits of the counter.

REFERENCES:
patent: 3651487 (1972-03-01), Washington
patent: 4419724 (1983-12-01), Branigan
patent: 4438507 (1984-03-01), Nakajima
patent: 4468753 (1984-08-01), Berger
patent: 4507732 (1985-03-01), Catiller et al.

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