Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2006-12-26
2006-12-26
Le, Thao X. (Department: 2814)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
07153707
ABSTRACT:
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide
itride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
REFERENCES:
patent: 3728694 (1973-04-01), Rohrer
patent: 3939292 (1976-02-01), Rohrer
patent: 4195355 (1980-03-01), Rohrer
patent: 4623912 (1986-11-01), Chang et al.
patent: 4782309 (1988-11-01), Benjaminson
patent: 4903110 (1990-02-01), Aono
patent: 4910578 (1990-03-01), Okamoto
patent: 4982309 (1991-01-01), Shepard
patent: 5005102 (1991-04-01), Larson
patent: 5046043 (1991-09-01), Miller et al.
patent: 5049517 (1991-09-01), Liu et al.
patent: 5049975 (1991-09-01), Ajika et al.
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5053917 (1991-10-01), Miyasaka et al.
patent: 5098860 (1992-03-01), Chakravorty et al.
patent: 5099305 (1992-03-01), Takenaka
patent: 5111355 (1992-05-01), Anand et al.
patent: 5134451 (1992-07-01), Katoh
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5168073 (1992-12-01), Gonzalez et al.
patent: 5171713 (1992-12-01), Matthews
patent: 5185689 (1993-02-01), Maniar et al.
patent: 5187638 (1993-02-01), Sandhu et al.
patent: 5189503 (1993-02-01), Suguro et al.
patent: 5198384 (1993-03-01), Dennison
patent: 5248628 (1993-09-01), Okabe et al.
patent: 5293510 (1994-03-01), Takenaka
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5366920 (1994-11-01), Yamamichi et al.
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 5387532 (1995-02-01), Hamamoto et al.
patent: 5391511 (1995-02-01), Doan et al.
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5396094 (1995-03-01), Matsuo
patent: 5401680 (1995-03-01), Abt et al.
patent: 5471364 (1995-11-01), Summerfelt et al.
patent: 5478772 (1995-12-01), Fazan
patent: 5489548 (1996-02-01), Nishioka et al.
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5561307 (1996-10-01), Mihara et al.
patent: 5631804 (1997-05-01), New
patent: 5796136 (1998-08-01), Shinkawata
patent: 5973344 (1999-10-01), Ma et al.
patent: 6030847 (2000-02-01), Fazan et al.
patent: 6066528 (2000-05-01), Fazan et al.
patent: 6071770 (2000-06-01), Roh
patent: 2005/0003609 (2005-01-01), Fazan et al.
patent: 2006/0138510 (2006-06-01), Fazan et al.
US 7,091,086, 08/2006, Fazan et al. (withdrawn)
Fujii, E. , et al., “ULSI DRAM technology with Ba/sub 0.7/Sr/sub 0.3/TiO/sub 3/ film of 1.3nm equivalent SiO/sub 2/ thickness and 10/sup -9/ A/cm/sup 2/ leakage current”,International Electron Devices Meeting 1992. Technical Digest, (1992),267-270.
Kaga, T , et al., “Crown-Shaped Stacked Capacitor Cell for 1.5-V Operation 64-Mb DRAMs”,IEEE Transactions on Electron Devices, 38, (Feb. 1991),255-261.
Koyama, K. , et al., “A Stacked Capacitor with (Ba/sub x/Sr/sub 1-x/)TiO/sub 3/ for 256M DRAM”,Technical Digest, International Electron Devices Meeting, (Dec. 8-11, 1991),823-826.
Wolf, “Silicon Processing for the VLSI ERA”,Process Integration, vol. I,(1989),169-171.
Fazan Pierre C.
Mathews Viju K.
Hafiz Mursalin B.
Le Thao X.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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