Apparatus and method for correcting signal imbalances using...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S321000

Reexamination Certificate

active

07069284

ABSTRACT:
A complex multiplier is described for filtering a signal in the frequency domain. In one embodiment, additional, independent frequency coefficients are supplied by the complex multiplier so that gain and/or phase of the signal may be independently modified (i.e., gain may be modified without affecting phase and vice-versa).

REFERENCES:
patent: 4015238 (1977-03-01), Davis
patent: 5027374 (1991-06-01), Rossman
patent: 5291499 (1994-03-01), Behrens et al.
patent: 5295142 (1994-03-01), Hatakeyama
patent: 5349608 (1994-09-01), Graham et al.
patent: 5608737 (1997-03-01), Kimura et al.
patent: 5778192 (1998-07-01), Schuster et al.
patent: 5907586 (1999-05-01), Katsuragawa et al.
patent: 5974095 (1999-10-01), Kitaura et al.
patent: 6005640 (1999-12-01), Strolle et al.
patent: 6044112 (2000-03-01), Koslov
patent: 6049573 (2000-04-01), Song
patent: 6119265 (2000-09-01), Hara
patent: 6122325 (2000-09-01), Mogre et al.
patent: 6138265 (2000-10-01), Morelos-Zaragoza et al.
patent: 6141391 (2000-10-01), Morelos-Zaragoza et al.
patent: 6148043 (2000-11-01), Fujimoto
patent: 6157997 (2000-12-01), Oowaki et al.
patent: 6189126 (2001-02-01), Ulmer et al.
patent: 6195642 (2001-02-01), Izumi et al.
patent: 6266687 (2001-07-01), Leyonhjelm et al.
patent: 6278725 (2001-08-01), Rouphael et al.
patent: 6301314 (2001-10-01), Murayama
patent: 6340883 (2002-01-01), Nara et al.
patent: 6563889 (2003-05-01), Shih et al.
patent: 0 762 777 (1997-03-01), None
patent: WO 00/74264 (2000-12-01), None
patent: WO 01/59937 (2001-08-01), None
Marilaure Boucheret, et al., “Fast Convolution Filter Banks for Satellite Payloads with On-Board Processing.” IEEE Journal On Selected Areas In Communications, vol. 17, No. 2, Feb. 1999.
W. H. Yim, et al. “On-Bard Processing for KA-Band Applications.” University of Surrey, UK, pp. 225-2259, Feb. 11, 1993.
Bree, et al., “A Bit-Serial Architecture For A VLSI Viterbi Processor”, Communications Systems Research Group, University of Saskatchewan, Saskatoon, IEEE, WESCANEX '88, 1988, pp. 72-77.
Biver, et al., “Architectural Design and Realization Of A Single-Chip Viterbi Decoder”, Elsevier Science Publishers B.V.,INTEGRATION, The VLSI Journal 8 (1989), Oct., No. 1, Amsterdam, NL, pp. 3-16.
Bree, et al., “A Modular Bit-Serial Architecture For Large Constraint-Length Viterbi Decoding”, Communications Systems Research Group, University of Saskatchewan, Saskatoon, Canada, IEEE International Conference on Communications, 1990, pp. 1501-1506.
Choi, et al., “Viterbi Detector Architecture For High-Speed Optical Storage”, 1997, IEEE TENCON—Speech and Image Technologies for Computing and Telecommunications, ASIC Center Corporate Technical Operations SAMSUNG Electronics, vol. 1, Dec. 1997, pp. 89-92.
W.H. Yim and F.P. Coakley, “On-Board Processing For KA-Band Applications”, University of Surrey, UK, Publication Date, Feb. 11, 1993., XP 000458011, pp. 225-229.
Hashida Mitsuyoshi, “Hierachical Network Management System and Control Method for Network Management Information,” Patent Abstracts of Japan, Publication No. 07226777, Aug. 1995.
James Tsui, Frequency Channelization, Digital Techniques for Wideband Receivers, Second Edition, pp. 363-396, 2001 Artech House, Inc., Norwood, MA.
E. Verriest, ISEN, Implementing an Adaptive Noise Canceling System to Enhance Sonar Receiver Performance Using the TMS320C31 DSP, ESIEE, Paris, Sep. 1996, Texas Instruments, pp. 1-24.
G.A. Shaw, R.A. Ford, J.C. Anderson, B.W. Zuerdnorfer, A.H. Anderson, RASSP Benchmark 2 Technical Description, Massachusetts Institute Of Technology Lincoln Library, 153 pages total., 1995.
“www.inventra.com/inventra/softcore/workshop/MultiRaFiltDes95/” Mentor Graphics, Hardware Design of Decimators/Interpolators, pp. 1-38., 1997.
“www.mentor.com/inventra/softcore/workshop/SDmod95/”, Mentor Graphics, Introduction to AD/DA Converters, pp. 1-27., 1997.
http://www.mentor.com/inventra/softcore/workshop/SDHWDes95/ Mentor Graphics, Design of the Decimation & Interpolation Filters, pp. 1-57., 1997.
http://www.mentor.com/inventra/softcore/workshop/Applications95/, Mentor Graphics, Sigma Delta Converter Applications, pp. 1-5., 1997.

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