Semiconductor memory device and memory card

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185050, C365S185170, C365S185230

Reexamination Certificate

active

07142453

ABSTRACT:
A semiconductor memory device disclosed herein comprises: a memory cell array including memory blocks, each memory block including memory cells arranged in a matrix and the memory cell array including first select gate transistors to select one or more memory cells; a select gate line configured to input a control signal which controls continuity of the first select gate transistor to a gate of the first select gate transistor, the select gate line being shared between two adjacent memory blocks; and a row select circuit configured to select a memory block of a row designated by an input address signal, wherein the row select circuit comprises: only one transfer transistor provided between the select gate line and a non-select signal line to which a non-select signal is supplied, the non-select signal being the control signal indicating non-selection; and a select gate control circuit configured to bring the transfer transistor into conduction to supply the non-select signal to the select gate line when both the two adjacent memory blocks are not selected.

REFERENCES:
patent: 5515327 (1996-05-01), Matsukawa et al.
patent: 6044017 (2000-03-01), Lee et al.
patent: 6853029 (2005-02-01), Ichige et al.
patent: 6891757 (2005-05-01), Hosono et al.
patent: 8-255494 (1996-10-01), None
patent: 11-238391 (1999-08-01), None

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