Memory having internal column counter for compression test mode

Details Memory having internal column counter for compression test mode Memory having internal column counter for compression test mode

2006-10-17

2006-10-17

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Counting

C365S189040, C365S189050

Reexamination Certificate

active

07123542

ABSTRACT:
A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating a compression register of expected data to compare to data read from the array of memory cells in response to a first read command, latch a second column address in response to a second read command while the first read command is executing, and provide the second column address for generating the compression register of expected data to compare to data read from the array of memory cells in response to the second read command once execution of the first read command is completed.

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A copy of PCT International Search Report for International Application No. PCT/EP2005/013934 mailed on May 22, 2006 (6 pages).

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