Nonvolatile semiconductor memory device, charge injection...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185240, C365S185260, C365S185270, C365S189090

Reexamination Certificate

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07092291

ABSTRACT:
A charge injection method for improving the efficiency of generating hot carriers, wherein, for example, electrons are injected at writing and holes are injected at erasing to a charge storage layer of a memory transistor. A positive voltage is applied to the drain region by using a voltage of the source region as a reference, and a voltage having a polarity in accordance with charges to be injected is applied to a gate electrode. A voltage having a voltage value between a source voltage and a drain voltage for turning on a diode made by an N-type source region and a P-type body region is applied to the body region. Then a parasitic bipolar transistor turns on, and, consequently, impact ionization arises on the drain side and an injection charge amount increases.

REFERENCES:
patent: 5999444 (1999-12-01), Fujiwara et al.
patent: 6301155 (2001-10-01), Fujiwara
patent: 6570788 (2003-05-01), Nakamura
patent: 2001-102553 (2001-04-01), None

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