Direct alignment scheme between multiple lithography layers

Details Direct alignment scheme between multiple lithography layers Direct alignment scheme between multiple lithography layers

2006-08-08

2006-08-08

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257SE27013, C257SE29026, C257SE23070

Reexamination Certificate

active

07087943

ABSTRACT:
A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

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VLSI Technology, edited by S.M. Sze, Copyright 1983—Bell Laboratories, Incorporated, Murray Hill, New Jersey; McGraw-Hill Book Company; ISBN 0-07-062686-3, McGraw-Hill series in electrical engineering, Electronics and electronic circuits; Lithography pp. 273-274.

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