Semiconductor storage device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185210, C365S185230, C365S201000

Reexamination Certificate

active

07095652

ABSTRACT:
A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a plurality of word lines connected to memory cells aligned on rows of the memory cell array; a plurality of sub-bit lines connected to memory cells aligned on columns of the memory cell array; a bit line select circuit selecting the sub-bit line of a column; a main bit line connected to the sub-bit line selected by the bit line select circuit; a sense line detecting the potential of the sub-bit line selected by the bit line select circuit via the main bit line and reading data out of the memory cell; a write driver applying a voltage to the sub-bit line selected by the bit line select circuit via the main bit line and writing data into the memory cell; and a first switching element connected to the main bit line and turning on when the current flowing in the memory cell is detected externally via the sub-bit line without the use of the sense line or when a voltage is applied to the memory cell externally via the sub-bit line without the use of the write driver.

REFERENCES:
patent: 5157627 (1992-10-01), Gheewala
patent: 5592425 (1997-01-01), Neduva
patent: 5612916 (1997-03-01), Neduva
patent: 6067253 (2000-05-01), Gotou
patent: 6621725 (2003-09-01), Ohsawa
patent: 2005/0265085 (2005-12-01), Kuo
patent: 2006/0062061 (2006-03-01), Suh et al.
patent: 10-241400 (1998-09-01), None
Takashi Ohsawa, et al., “Memory Design Using One-Transistor Gain Cell on SOI”, 2002 IEEE ISSCC, Digest of Technical Papers, Feb. 5, 2002, pp. 152-153.

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