High speed biCMOS gate power for power MOSFETs incorporating imp

Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Plural non-isolated transistor structures in same structure

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Details

257557, 257565, 257197, 257578, H01L 2900, H01L 27082, H01L 27102, H01L 310328

Patent

active

06034413&

ABSTRACT:
A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages. The circuit can tolerate negative voltages up to approximately two diode drops on its output and gate drive terminals because (a) when transistor Q2 is conducting it is effectively configured as an NPN diode and the collector cannot sustain a voltage less than one base-emitter drop above its emitter, (b) transistor M13 is a DMOS transistor which can withstand negative voltages upon its source when it is nonconducting due to the interposition of the backgate between the source and the drain and (c) transistors M17 and M18 are returned to ground and not to the output terminal.

REFERENCES:
patent: 5144409 (1992-09-01), Ma
patent: 5666001 (1997-09-01), Miwa
patent: 5734183 (1998-03-01), Morishita
patent: 5828124 (1998-10-01), Villa

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