Method and circuit for adjusting the timing of output data...

Details Method and circuit for adjusting the timing of output data... Method and circuit for adjusting the timing of output data...

2006-11-21

2006-11-21

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

C375S355000, C375S356000

Reexamination Certificate

active

07139345

ABSTRACT:
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

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