Power-on reset circuit

Details Power-on reset circuit Power-on reset circuit

1987-07-16

1988-11-29

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307362, 307443, 307448, H03K 301, H03K 5153, H03K 1716, H03K 19017

Patent

active

047884541

ABSTRACT:
A reset circuit for a logic circuit comprises a MOS transistor having a gate coupled to a power supply, a source receiving a reset input and a drain whose potential is high when the reset input is high and the power supply voltage drops below a predetermined threshold, a flip-flop connected to be set when the drain of the MOS transistor is high and reset when the reset input is low, and a circuit producing a reset output when the flip-flop is in the set state, the reset output being applied to the logic circuit.

REFERENCES:
patent: 4103187 (1978-07-01), Imamura
patent: 4366560 (1982-12-01), McDermott et al.

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