Method for forming gang bonding bumps on integrated circuit semi

Details Method for forming gang bonding bumps on integrated circuit semi Method for forming gang bonding bumps on integrated circuit semi

1975-05-19

1977-08-16

Kendall, Ralph S.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 89, 427 91, 427261, 29589, 29630R, 428901, B05D 512, H01L 2348

Patent

active

040429547

ABSTRACT:
Gang bonding bumps, for making electrical connection to a metallic intraconnect pattern of metallization on an integrated circuit semiconductive device, are adhered to the interconnect pattern via the intermediary of a series of transition layers. These transition layers include a first layer of chromium, vacuum evaporated over the metallic interconnect pattern for providing a tightly adherent connection thereto. A layer of aluminum and chromium is vacuum evaporated over the chromium layer. A second layer of chromium is vacuum evaporated over the aluminum and chromium layer and a gold layer is deposited overlaying the chromium layer. The gold layer interfaces with the electroplated layers of the bump, which in a preferred embodiment consists of a lower layer of nickel covered by a layer of copper.

REFERENCES:
patent: 3480841 (1969-11-01), Castrucci et al.
patent: 3622385 (1971-11-01), Stork
patent: 3706015 (1972-12-01), Schimmer et al.

Affiliated with

Also associated with

Rating

Method for forming gang bonding bumps on integrated circuit semi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming gang bonding bumps on integrated circuit semi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming gang bonding bumps on integrated circuit semi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-364993