Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-05-02
2006-05-02
Mai, Son (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S154000
Reexamination Certificate
active
07038925
ABSTRACT:
Above a memory block including horizontal memory cells in 8 rows by 256 columns, a total of eight lines, a global word line, a bit line load power supply line, a local data input/output line pair, a bit line signal input/output line pair, a memory cell power supply line and a global column selecting line are, arranged at equal intervals. Since provision of one line is enough per one memory cell row, an SRAM having a T-type bit line structure can be realized with ease using horizontal memory cells to enable reduction of a layout area and speed-up of an operation rate.
REFERENCES:
patent: 5699308 (1997-12-01), Wada et al.
patent: 5808930 (1998-09-01), Wada et al.
patent: 5896340 (1999-04-01), Wong et al.
patent: 6009010 (1999-12-01), Ohkubo
patent: 6088276 (2000-07-01), Ukita
patent: 6288925 (2001-09-01), Kitsukawa
patent: 6317353 (2001-11-01), Ikeda et al.
patent: 5-63091 (1993-03-01), None
patent: 9-162305 (1997-06-01), None
patent: 9-270468 (1997-10-01), None
patent: 11-306762 (1999-11-01), None
“A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization”, by Kohno et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5 (Oct. 1988), pp. 1060-1066.
Mai Son
McDermott Will & Emery LLP
Renesas Technology Corp.
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