Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2006-10-24
2006-10-24
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S776000, C438S622000
Reexamination Certificate
active
07126222
ABSTRACT:
A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.
REFERENCES:
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5444022 (1995-08-01), Gardner
patent: 5510651 (1996-04-01), Maniar et al.
patent: 5571751 (1996-11-01), Chung
patent: 5614764 (1997-03-01), Baerg et al.
patent: 5666007 (1997-09-01), Chung
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5691572 (1997-11-01), Chung
patent: 5798299 (1998-08-01), Chung
patent: 5863835 (1999-01-01), Yoo et al.
patent: 5864179 (1999-01-01), Koyama
patent: 5889328 (1999-03-01), Joshi et al.
patent: 5939788 (1999-08-01), McTeer
patent: 5969422 (1999-10-01), Ting et al.
patent: 5981377 (1999-11-01), Koyama
patent: 6008117 (1999-12-01), Hong et al.
patent: 6008118 (1999-12-01), Yeh et al.
patent: 6030896 (2000-02-01), Brown
patent: 6037250 (2000-03-01), Matsubara
patent: 6037278 (2000-03-01), Koyangi et al.
patent: 6040627 (2000-03-01), Harada et al.
patent: 6077774 (2000-06-01), Hong et al.
patent: 6093635 (2000-07-01), Tran et al.
patent: 6133139 (2000-10-01), Dalal et al.
patent: 6759747 (2004-07-01), Harada
Dual Damascene: A ULSI Wiring Technology; Carter W. Kaanta et al; VMIC Conference, Jun. 11-12, 1991, pp. 144-152.
1991 Proceedings Eighth International IEEE, VLSI Multilevel Interconnection Conference; Ronald E. Uttecht and Robert M. Geffken; Jun. 11-12, 1991; pp. 20-26.
Copper Interconnections and Reliability; C.-K. Hu, J.M.E. Harper, Jun. 23, 1997, Materials Chemistry and Physics 52 (1998) 5-16.
Filling Dual Damascene Interconnect Structures with AlCu and Cu Using Ionized Magnetron Deposition; S.M. Rossnagel; J.Vac.Sci Technol. B 13(1) Jan./Feb. 1995, pp. 125-129.
Electrical Characterization of Tungsten Vias Planarized by CMP; D.L. Hetherington et al.; Conference Proceedings ULSI XI; 1996 Materials Research Society; pp. 757-762.
Submicron Wiring Technology with Tungsten and Planarization; Carter Kaanta et al.; Fifth International IEEE, VLSI Multilevel Inter. Conf; 1988; pp. 21-28.
Evaluation of Borderless Vias For Sub-Half-Micron Technologies; Henry W. Chung and Dah-Bin Kao; Jun. 27-29; 1996 VMIC Conference; pp. 667-669.
Electromigration Improvements With Titanium Underlay and Overlay in Al(Cu) Metallurgy; J.J. Estabil et al.; Jun. 11-12, 1991 VMIC Conf. pp. 242-248.
High Density Damascene Wiring and Borderless Contacts for 64 M DRAM; S. Roehl et al., Jun. 9-10, 1992, VMIC Conference; pp. 22-28.
High Stud-To-Line Contact Area in Damascene Metal Processing; IBM Technical Disclosure Bulletin; vol. 33, No. 1A, Jun. 1990; pp. 160-161.
Fahmy Wael
Oki Electric Industry Co. Ltd.
Peralta Ginette
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3646764