Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2006-02-21
2006-02-21
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S215000, C712S219000, C712S244000, C711S169000, C713S401000, C713S601000
Reexamination Certificate
active
07003650
ABSTRACT:
A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.
REFERENCES:
patent: 4722049 (1988-01-01), Lahti
patent: 5257214 (1993-10-01), Mason et al.
patent: 5907694 (1999-05-01), Suzuki et al.
Babaian Boris A.
Gorokhov Valeri G.
Gruzdov Feodor A.
Rudometov Vladimir V.
Sakhin Yuli K.
Elbrus International
Pan Daniel H.
Townsend and Townsend And Crew LLP
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