Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2006-02-28

2006-02-28

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250

Reexamination Certificate

active

07006385

ABSTRACT:
A nonvolatile memory device includes a memory cell array, a control circuit, a voltage boost circuit, a timer circuit, a discharge circuit and a sensor circuit. The control circuit generates an erase execution (EE) signal in response to an erase command (EC) signal, stops the EE signal and generates a discharge control (DC) signal in response to an erase termination (ET) signal, stops the DC signal in response to a discharge termination (DT) signal, and stops the EE signal and the DC signal in response to a reset signal. The boost circuit provides high voltage in response to the EE signal. The timer circuit generates the ET signal after receiving the EE signal. The discharge circuit discharges the high voltage and the sensor is enabled in response to the DC signal or the reset signal. The sensor generates the DT signal when the high voltage drops to a predetermined voltage.

REFERENCES:
patent: 6747902 (2004-06-01), Seki et al.
patent: 6909639 (2005-06-01), Park et al.
patent: 2000-100183 (2000-04-01), None

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