Power efficient booth recoded multiplier and method of...

Details Power efficient booth recoded multiplier and method of... Power efficient booth recoded multiplier and method of...

2006-06-27

2006-06-27

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S628000

Reexamination Certificate

active

07069290

ABSTRACT:
In the multiplier, a partial product circuit generates a partial product based on a multiplicand operand and outputs of a Booth recoder circuit, which operates on a multiplier operand. The partial product circuit ANDs the multiplicand with a zero Booth recoded output, which indicates whether to zero out the multiplicand. An enable circuit selectively enables the multiplier circuit, and more particularly, disables the multiplier circuit by making the zero Booth recoded output indicate to zero out the multiplicand.

REFERENCES:
patent: 5661673 (1997-08-01), Davis
patent: 5787029 (1998-07-01), de Angel
patent: 6065032 (2000-05-01), Nicol
patent: 6275842 (2001-08-01), Nicol
Weste, N. et al.Principles of CMOS VLSI Design, 2ndEdition, 1992, pp. 291-292, 304-305, 547-555.

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