Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2006-11-28
2006-11-28
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C257SE21509
Reexamination Certificate
active
07141453
ABSTRACT:
To make it possible to utilize both surfaces of a wafer, a wafer (1) is provided with a through hole (2) between upper and lower surfaces, an insulating layer (14) is formed in an inner surface of the through hole (2), rewiring circuits (3, 4) are formed on both the upper and lower surfaces, the rewiring circuits (3, 4) are connected by a plating (9) applied on the insulating layer (14) within the through hole (2), thermal stress relaxing posts (5, 6) are formed on the rewiring circuits (3, 4) by a conductive material such as a solder bumps (7, 8) are formed on the thermal stress relaxing posts (5, 6), and the solder bump (7) or (8) is connected to a wiring circuit (12) of a printed wiring substrate (11).
REFERENCES:
patent: 5962917 (1999-10-01), Moriyama
patent: 5981311 (1999-11-01), Chia et al.
patent: 6026564 (2000-02-01), Wang et al.
Bacon & Thomas PLLC
Chaudhari Chandra
Minami Co. Ltd.
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