Multi-stage numeric counter oscillator

Details Multi-stage numeric counter oscillator Multi-stage numeric counter oscillator

2006-06-20

2006-06-20

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S016000, C327S105000, C375S302000, C708S271000, C708S276000

Reexamination Certificate

active

07064616

ABSTRACT:
A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.

REFERENCES:
patent: 2005/0135524 (2005-06-01), Messier
patent: 0 312 370 (1989-04-01), None
patent: 0 416 869 (1991-03-01), None
patent: 0 459 446 (1991-12-01), None
patent: 1 215 558 (2002-06-01), None
European Search Report, Mailing Date Mar. 17, 2005.

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