Method of forming damascene pattern in a semiconductor device

Details Method of forming damascene pattern in a semiconductor device Method of forming damascene pattern in a semiconductor device

2006-06-27

2006-06-27

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S634000, C438S691000

Reexamination Certificate

active

07067431

ABSTRACT:
The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides of the via holes to a prescribed thickness, forming an anti-reflection layer on the via holes and the insulating layer, forming a mask pattern for trench etching on the insulating layer on which the anti-reflection layer is formed, and forming a damascene pattern using the mask pattern for trench etching. CD uniformity is improved by minimizing change of the critical dimension of the damascene pattern, thereby increasing reliability of the semiconductor device.

REFERENCES:
patent: 5635423 (1997-06-01), Huang et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 6251774 (2001-06-01), Harada et al.
patent: 6365529 (2002-04-01), Hussein et al.
patent: 6576550 (2003-06-01), Brase et al.
patent: 10-2001-0059540 (2001-07-01), None

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