Method for integrated circuit device isolation

Details Method for integrated circuit device isolation Method for integrated circuit device isolation

1984-01-12

1985-09-17

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148DIG50, H01L 2176

Patent

active

045411670

ABSTRACT:
The disclosure relates to a method manufacturing semiconductor devices which minimizes encroachment by utilizing a polycrystalline silicon (polysilicon) layer over a grown oxide on the substrate with a nitride layer positioned above the polysilicon layer. A patterned resist is then formed in the active device regions and the device is then etched in the regions where the resist has not been applied to remove the nitride layer, the polysilicon layer and the oxide layer in one embodiment and, in a second embodiment, also removes a portion of the substrate. The silicon substrate portion which is exposed is then oxidized by field oxidation to provide, in the first embodiment, an oxide layer which rises above the level of the polysilicon layer and, in the second embodiment, to a point equal to or slightly above the oxide layer beneath the polysilicon layer. The nitride and polysilicon layer are then stripped or, alternatively, the polysilicon layer can be oxidized. The oxide layer in the active region is then etched back to the silicon layer and a gate oxide is then formed in the active region in standard manner. The processing then continues in standard manner to provide an MOS or bipolar device. The above noted procedure provides active semiconductor devices with essentially no encroachment or "bird beak" problem present. The procedure can also be used with elimination of the first oxide layer over the substrate.

REFERENCES:
patent: 3900350 (1975-08-01), Appels et al.
patent: 4419142 (1983-12-01), Matskawa
patent: 4441941 (1984-04-01), Nozawa

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