Process for formation of shallow silicided junctions

Details Process for formation of shallow silicided junctions Process for formation of shallow silicided junctions

1987-03-31

1988-11-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 30, 437931, 437192, 148DIG105, 148DIG147, H01L 21265

Patent

active

047881607

ABSTRACT:
A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.

REFERENCES:
patent: 4259680 (1981-03-01), Lepselter et al.
patent: 4339869 (1982-07-01), Reihl et al.
patent: 4450620 (1984-05-01), Fuls et al.
patent: 4505027 (1985-03-01), Schwabe et al.
patent: 4558507 (1985-12-01), Okabayashi et al.
patent: 4597163 (1986-07-01), Tsang
H. Okabayashi et al., "Low Remittance MOS . . . ", IEDM 1982, pp. 556-559.

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